Evolution of the multi-core processor architecture Intel Core: Conroe, Kentsfield...
Undoubtedly, one of the most interesting IT intrigues of this
season is the forthcoming announcement of a new generation of the
multicore processor architecture Intel Core. Due to Intel's benevolent
PR policies on the whole and open contacts with the press in
particular, we've known so much about these chips already now, before
the official announcement of various processor models. At least this is
more than enough that today we are presenting to our readers' attention
a review of the architectural changes and improvements implemented in
the new generation of processors built on the Intel Core architecture.
It's no longer a secret for anyone that the new dual-core
processors having the working names Merom, Conroe, and Woodcrest for
the markets of mobile, desktop and server computers, respectively, will
have the unified architectural framework under the consolidated name Intel
Core (formerly named as Architecture 101),
with some additions meeting specific requirements of each market
sector. Nevertheless, while presenting the new generation architecture
Intel Core, we'll be making the major focus on the chips for desktop
PCs the Conroe.
Let me put it straight that the story deals solely with the
architectural features of Intel's new processors. Therefore, it makes
no sense to expect any rumors, leakages or hints regarding the marking
of Conroe chips, timelines of their announcements and arrival to the
retail, expected prices, etc. The most what the author allowed for
himself within this story is assumptions of the probable performance
boost at specific applications.
All the other information accompanied by comparative tests of
the new chips will be presented to our readers in due time. Now it is
just the very moment when it's "better be safe than sorry" and present
only authentic information rather than spreading gossip prematurely. I
hope our readers, after "digesting" the architectural features of
Intel's new generation of processors, will be able not only
scrutinizing the "marks" in a laid-back way, but also get a better idea
of the causes and consequences which lead to a specific result. Let's
start.
Basic formulas defining the efficiency of modern processor
architecture
As is known, a few years ago Intel gave up the idea of
"boosting megahertz" and headed towards development of efficient
processor micro architectures of economical power consumption. In this
regard, the maximum operating efficiency of the processor is more
dependent directly on the number of instructions executed per cycle
rather than the clock speed. In other words, the processor's clock sped
is merely one of the factors in this simple formula:
[Performance] = [Clock speed] x [Number of
instructions per cycle]
Therefore, in practice you don't have to boost up the clock
speed - there are many other effective methods to raise performance
substantially. One of the subsets of such methods in particular is the
use of currently so popular multicore processing, although, as the
practice shows, it's not an easy task to parallelize computations among
a number of cores and it can't be "brute-forced".
 Another rather effective method to raise one of the factors in
the above formula for performance calculation is the method for
reducing the number of instructions required to run a specific task or,
in other words, the command thread optimization. The most visual
example of that is the MMX SIMD-commands (single instruction multiple
data) used by Intel in the form of integer 64-bit SIMD instructions
since 1996, starting with Pentium chips supporting the MMX, as well as
the later introduced 128-bit SIMD floating-point single precision
instructions which were first presented in the SSE SIMD-extensions in
the Pentium III chip later complemented by SSE2 and SSE3 instruction
sets.
Another bright example of the command thread optimization
technology is the so-called microfusion technology implying that a
number of internal micro-ops of the CPU can be merged into a single
micro-op, which substantially reduces the total number of micro-ops
required to run a specific task.
At the same time, the current mindset in the industry aimed at
production of economical processors requires other computations.
Therefore, there has been introduced the concept of optimum
performance, which reflects the quantity of energy spent by
the CPU to run a specific task. It turns out that the power consumption
can be estimated as a product of dynamic capacitance (a ratio of the
electrostatic charge of the conductor to the potential between
conductors which provide the charge) and the efficiency of executing
instructions per cycle, squared supply voltage, and the clock speed:
[Power consumption] = [Dynamic capacity] x [Voltage]
x [Voltage] x [Clock speed]
Correlating this equation for the calculation of power
consumption versus the previous formula, processor developers will be
able to better estimate the optimum balance between the efficiency of
the number of instructions executed per cycle, dynamic capacitance, on
the one hand, and appropriate supply voltage for the core and buffer
circuits in combination with the chip's clock speed, on the other hand.
This will let achieve the optimum performance and efficient power
consumption.
I apologize for the long-drawn introduction and explanation of
the copy-book truth, but this prelude will let you understand the goals
and methods used in the development of the new-generation micro
architecture Intel Core that offers improved performance and, most
importantly, improved per-watt performance.
Main features of the Intel Core architecture
The most precise, authentic and detailed information on the
inner structure of Intel's new-generation processors for desktop PCs
which are expected to emerge in the nearest future was made public
during the spring forums arranged by Intel for developers - Intel
Developer Forum, and during the Moscow IDF Spring 2006, in particular.
It was just the first time when Intel distinctly pronounced its plans
to start deliveries of processors on the base of the Intel Core
architecture with the 65-nm process technology already in the third
quarter of 2006. That was just the time when it became known for sure
that the new architecture will be the framework for processors of all
the market sectors desktop PCs (Conroe), mobile PCs
(Merom), and servers (Woodcrest).
The new chips built on the Intel Core architecture promise a
substantial performance boost - from 40% for Conroe up to 80% for
Woodcrest, with the power consumption reduced by 35-40%.
That the materials explaining the essence of these innovations
have appeared on our site only now is caused by a number of reasons.
First, Intel has finally finished rebranding the processor lines and
now we can state with confidence that the new chips for desktop PCs
will be represented just by the trade marks Intel Core 2
Extreme (Conroe XE) and Intel Core 2 Duo
(Conroe, Merom). Secondly, the time passed since the spring IDF has
allowed to comprehend the architectural changes and sort out with the
operational specifics in order to present the essence of these
novelties to our readers at maximum authenticity. Thirdly, Computex
2006 held in the first decade of June, where working prototypes of
systems built on the base of Conroe chips were presented, has put
everything in the right places: the new-generation architecture has
been around for quite a long time not only on paper but also in the
form of specimens ready for retail sales. So it is quite possible that
selection of the forthcoming date for announcement of Conroe chips is
caused more by "marketing policies" considerations rather than
production aspects.
The new processor architecture inherits the philosophy of
effective power consumption first implemented in Intel Pentium M
processors for mobile PCs having the working name Banias. The
functional capabilities of the new-generation processors have been
improved not only due to the new technologies but also due to the
developments successfully used in the chips of the Intel NetBurst
architecture. Nevertheless, the key role is played by the innovations
first implemented in Intel's new-generation architecture:
- The Intel Wide Dynamic Execution
technology is to provide a greater number of instructions executed per
cycle, thus improving the efficiency of running applications and
reducing the power consumption. Each core of the processor that
supports this technology is now able executing up to four instructions
simultaneously using the 14-stage pipeline.
- The Intel Intelligent Power Capability
that enables specific components of the chip only when needed allows to
achieve a substantial reduction in the power consumption of the system
on the whole.
- The Intel Advanced Smart Cache
technology implies using a unified L2 cache memory common for all the
cores, whose joint use allows to cut down the power consumption and
raise the performance. At the same time, one of the processor cores may
use up the whole volume of the cache memory whenever needed, with the
other core disabled dynamically.
- The Intel Smart Memory Access
technology increases the system performance due to the reduced memory
response time and thus optimized bandwidth of the memory subsystem.
- The Intel Advanced Digital Media Boost
technology allows processing all the 128-bit SSE, SSE2, and SSE3
commands widely used in multimedia and graphic applications in one
cycle, which increased their speed of execution.
These are the major changes introduced into the new generation
of the Intel Core micro architecture. It is now time we dwelled on each
of them.
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