Evolution of the multi-core processor architecture Intel Core: Conroe, Kentsfield...
Intel Wide Dynamic Execution
The Intel Wide Dynamic Execution
technology implies a set of novelties – advanced data
analysis, speculative, priority-oriented command execution etc.first
implemented by Intel in the P6 architecture and used in Pentium Pro,
Pentium II, and Pentium III. In the Intel NetBurst architecture, the
Advanced Dynamic Execution module was used for these purposes, which
provided load to the executive modules of the processor and offered an
improved branch processing algorithm in order to reduce the number of
wrong branch predictions.
At the level of the Intel Core architecture, all this is
consolidated into the advanced technology complex named the Intel Wide
Dynamic Execution which allows providing greater number of commands
executed per cycle, thus saving the time and energy.
Now each processor core is able processing not three as it was
in the Intel NetBurst architecture but four commands at a time, which
gives a 33% boost as compared to the previous generations. Among the
additional features implemented in the set of Intel Wide Dynamic
Execution technologies, of note is the more precise branch prediction
and deeper command buffering, which imparts additional flexibility to
the execution process.
Along with these, Intel Wide Dynamic Execution implies an
efficient use of the Macro-Fusion technology (Macro-OPs Fusion) that
merges micro- and macro operations into unified executable macro
operations. While in the previous generations of Intel processors each
incoming instruction was decoded and executed separately, now the use
of the macro-fusion principle during the command decoding allows
merging pairs of some instructions into a unified internal micro-op.
Execution of two instructions as a unified micro-op allows
reducing the total CPU usage and increasing the number of instructions
processed per cycle. Moreover, the Arithmetic Logic Units used in Intel
Core processors have been improved for better processing the commands
merged into the macro-ops, which also results in the overall reduction
of the chip's power consumption.
Therefore, according to Intel, it becomes possible to reduce load on
operations by up to 15% and cut sown the number of micro operations by
up to 10%, in the general case. As can be seen on the below diagram,
the prefetch modules prepare a number of x86 commands, and up to five
of them can be processed by four decoding units simultaneously. In the
case of Macro-Fusion, it becomes possible to process five instructions
per cycle at a time (no more than one macro command can be generated at
a time).
Intel Intelligent Power Capability
Another innovation under the consolidated name Intel
Intelligent Power Capability appears to be a set of measures
aimed at the reduction of power consumption of the chip and
optimization of general design requirements. Technologies coordinating
the power consumption by all the executable units of the processor
include advanced features optimized for access time which keep track of
the load at specific logical circuits.
It is important to note that load reduction in the Intel Core
architecture is done not through disabling unused circuitry;
on the contrary – the trace logic of the Intel Intelligent
Power Capability enables the required logical
subsystems once they are needed. Additionally, many inner buses and
arrays of the CPU logical units are now distributed and powered through
separate keys, which made it possible to switch them into the
additional economical power-saving mode while processing certain types
of data.
The major task of such "point-of-use" power scheme was to
achieve a fast system response, e.g. when reverting the system back to
the full capacity mode. As a result, such weighted approach in
implementing the Intel Intelligent Power Capability has made it
possible to further reduce the power consumption without detriment to
the system response speed and increase the total power optimization of
the Intel Core architecture.
Intel Advanced Smart Cache
The new Intel Core architecture implements a rather efficient
model of shared use of common L2 cache by the CPU cores. The Intel
Advanced Smart Cache technology is optimized in a way allowing each
core of the dual-core processor access data at the maximum efficiency.
Not all modern multicore processors are able distributing
access to the shared L2 cache memory. In practice it means that each
core has to operate with similar data placed in its own L2 cache.
Moreover, the downtime of one of the cores in using the scheme of
separate L2 caches simply means a downtime of the L2 cache memory in
this core, which results in inefficient use of resources –
whereas the second core may be running "breathless" without additional
resources of the L2 cache.
In the case of the Intel Core architecture, both the cores
access the common L2 cache and are able redistributing – up
to 100%! - of L2 cache resources dynamically depending on the current
load. This Multi-Core Optimized Cache technology allows for optimum use
of the cache memory resource subsystem. Additional advantage of the
Multi-Core Optimized Cache is in the much faster fetching of data out
of the cache.
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